1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular, to a method wherein a step of forming an electrode in a semiconductor integrated circuit (IC) has been improved.
2. Description of the Related Art
There is known a direct contact method as a method of forming an electrode in a semiconductor IC. FIG. 2 is a partial cross-sectional view of a conventional semiconductor IC manufactured by the direct contact method, showing a drain region of a MOS transistor (MOS FET) serving as an element of a static RAM or a mask ROM. An N-type diffusion region 32 is formed in a major surface of a P-type substrate 31. The region 32 becomes a drain region exposed to the substrate 31. Then, an insulating film 33 is deposited on the substrate 31. An opening is formed in the insulating film 33 so as to reach the diffusion region 32. A polycrystalline silicon layer is deposited over the resulting structure by a CVD (Chemical Vapor Deposition) method. The polycrystalline silicon layer is patterned to form a wiring layer 34.
When the above-described method is used, it is difficult, however, to sufficiently reduce an electric resistance or a contact resistance between the polycrystalline silicon wiring layer 34 and the drain region 32.
As a conventional method capable of reducing the electric resistance, a method, as illustrated in FIGS. 3A to 3C, has been proposed. In FIG. 3A, an N-type diffusion region 42 is formed in a major surface of a P-type substrate 41. The region 42 becomes a drain region exposed to the substrate 41. Then, an insulating film 43 is deposited on the substrate 41. An opening 45 is formed in the insulating film 43 so as to reach the drain region 42. In FIG. 3B, by using a selective epitaxial growth method, the opening 45 is filled with a single-crystal silicon layer 46 containing N type impurities. Thereafter, as shown in FIG. 3C, a polycrystalline silicon layer is deposited on the resulting structure, and is patterned to form a wiring layer 44.
According to this method, the low-resistance silicon layer 46 containing the impurities serves to reduce the electric resistance between the wiring layer 44 and the drain region 42.
However, the formation of the silicon layer with use of the selective growth method incurs problems relating to the prevention of precipitation of silicon on the insulating layer, the removal of precipitated silicon, etc. If parameters of conditions for the selective growth, such as reaction gas density or temperature, are set to optimal values, and cleanness in the reaction vessel is maintained, the possibility of precipitation of silicon on the insulating film is kept low, and no problem would occur.
Continuous selective growth would sometimes make it difficult to maintain the above ideal conditions. Consequently, silicon is precipitated on the insulative layer. Further, polycrystalline silicon is deposited on the precipitated silicon to form a projection. In this case, it is difficult to fatten or eliminate the projection. The precipitated silicon may cause a shortcircuit in the wiring, and the manufacturing yield of semiconductor devices decreases considerably.
FIG. 4 is a cross-sectional view of another conventional semiconductor device manufactured by the above-described selective growth method. This semiconductor device is a dynamic RAM. FIG. 4 shows, in particular, an area including a drain region of a MOS transistor which constitutes the dynamic RAM. An N-type diffusion region (drain region) 52 is formed in a P-type substrate 51 so as to be exposed to the surface of the substrate 51. A silicon oxide film 53a and a BPSG (boron-phospor-silicon glass) film 53b are sequentially deposited on the substrate 51. An opening is formed in the silicon oxide film 53a and the BPSG film 53b, and a silicon layer 56 containing impurities is filled in the opening by the selective growth method. Thereafter, an aluminum-silicon alloy layer is deposited on the resulting structure, and the alloy layer is patterned to form a wiring layer 54.
Like the method shown in FIGS. 3A to 3C, this method is effective in reducing the electric resistance between the drain region 52 and the wiring layer 54. However, in this method, similar problems remain to be solved. Namely, dust of several .mu.m adheres to the surface of the BPSG film, in the process of filling the opening with the silicon layer 56 by the selective growth method. The dust originates from a silicon thin film deposited on the inner wall of the growth apparatus, or from a quartz or silicon oxide film forming the inner wall of the apparatus. The silicon growth is normally performed in a vessel having a reduced pressure. Thus, the silicon thin film or the silicon oxide film is easily peeled at the time of supplying/exhausting the air in/from the vessel. The peeled film is attached on the surface of the BPSG film 53b. In addition, during the selective growth, the substrate is heated up to 900.degree. C. As a result, the BPSG film 53b is melted, and dust attached on the surface of the BPSG film 53b is more firmly attached on or in the film 53b. In the process of depositing the aluminum-silicon alloy layer, subsequent to the process of selective growth of single-circuiting silicon layer 56, the dust attached firmly adhered on the underlying BPSG film 53b causes deficiencies in the wiring layer 54, such as interlayer short-circuiting or breaking of wire.
Dust of the particle size of 1/10 or more of a distance between wires may cause deficiencies in the wiring layer, and this problem becomes more significant as the number of integrated elements increases.
As described above, the direct contact method of forming an electrode connected to the diffusion layer cannot sufficiently reduce the electric resistance at the contact portion. This problem may be solved by the method of forming the opening in the interlayer insulative layer on the diffusion region, filling the silicon layer in the opening by the selective vapor deposition process, and forming the electrode. This method has been widely used with the miniaturization of elements. However, when the silicon layer is filled in the opening by the selective vapor deposition, silicon may be precipitated on the insulative layer or dust may be adhered thereon, resulting in the deficiency in wiring, such as an interlayer short-circuit, and the lowering in the manufacturing yield.